Role at a Glance
This Bristol-based role places you at the core of Graphcore's AI hardware electrical design. You will own signal integrity from early simulation through prototype bring-up and into manufacturing, covering 112 Gbps and 224 Gbps SERDES, DDR, and processor interfaces. Essential tools include ANSYS HFSS/SIWave and Mentor HyperLynx. Salary is not disclosed; confirmed package elements include a matched pension and phantom equity.
What This Role Is About
Graphcore needs an engineer to take full ownership of signal integrity across its AI hardware platforms, from early-stage simulation all the way through prototype bring-up and into production support. Day-to-day work spans PCB structure extraction and modelling, transmission line and via design, stack-up and material selection, and then correlating those simulated results with measured lab data. The position sits inside the Bristol Hardware Engineering team and operates at the intersection of electromagnetic simulation, physical board design, and ongoing collaboration with PCB layout, package substrate, and system architecture specialists.
About Graphcore
Graphcore is a Bristol-founded AI compute company, now part of the SoftBank Group, that designs specialised silicon and system infrastructure built specifically for demanding AI workloads rather than adapted from general-purpose processors. Its engineering community draws from AI research, silicon design, software, and systems architecture, working in close proximity to ship hardware that operates at datacentre scale. The company's stated aim is to accelerate AI adoption across every industry, positioning it among the more technically ambitious employers in the UK semiconductor and AI infrastructure space. Employees participate in that upside through a phantom equity programme tied to company performance.
What You Will Be Doing
- Develop, extract, and simulate PCB structures for production systems and test boards targeting 112 Gbps and 224 Gbps SERDES, DDR, and processor interfaces
- Define via structures, BGA and connector launches, transmission line geometries, and stack-up configurations to meet GHz-range performance budgets
- Select low-loss dielectric materials and validate choices against system-level insertion-loss and timing constraints
- Own signal integrity decisions across complex board and package interfaces from concept through to prototype bring-up
- Conduct lab measurements with VNAs, high-bandwidth oscilloscopes, and signal generators to correlate simulation models against hardware behaviour
- Contribute to design reviews by communicating signal integrity constraints and trade-offs to PCB layout, substrate, and system architecture teams
- Drive debug and root-cause analysis during prototype phases, then carry validated solutions through to manufacturing support
What You Must Bring
- Proven depth in high-speed digital circuit development covering both signal and power integrity analysis
- Hands-on experience designing and validating high-frequency SERDES links operating at tens of GHz, including interfaces at 112 Gbps or above
- Working proficiency with at least one major EM solver — ANSYS SIWave, ANSYS HFSS, Mentor HyperLynx, or a comparable tool
- Demonstrated ability to design BGA launches, connector transitions, via structures, and controlled-impedance transmission lines for GHz-range signals
- Bench skills with VNAs, high-bandwidth oscilloscopes, and signal generators for S-parameter measurement and waveform capture
- Strong ownership approach to design, debug, and validation, paired with clear communication skills for cross-functional design reviews
Skills Breakdown and Seniority Context
The technical core of this position is electromagnetic simulation paired with measurement-backed validation of ultra-high-speed serial links. Must-haves include hands-on proficiency with at least one major EM solver (ANSYS SIWave, HFSS, or HyperLynx), the ability to characterise channel loss and discontinuities at tens of GHz, and bench experience capturing S-parameters with a VNA. Power integrity appears alongside signal integrity as an explicit requirement, so candidates with PDN analysis experience will be competitive. The level of autonomy described — independently owning signal integrity decisions across complex board and package interfaces — points clearly to a senior-level profile rather than a graduate or mid-level position.
Salary and Compensation
No salary figure is published for this role. Graphcore has not provided a range in the listing, and JobForMe does not estimate or infer pay not stated by the employer. Candidates should raise compensation directly at the initial recruiter or hiring manager call. What the listing does confirm: a matched pension contribution of up to 5% of salary and phantom equity participation, which links employee financial upside to a Graphcore liquidity event such as an acquisition or public offering. The flexible benefits envelope adds optional private medical insurance and dental cover, which carry meaningful value beyond base pay.
Benefits Package
- Flexible working arrangements
- Generous annual leave
- Matched pension contribution of up to 5%
- Phantom equity — financial participation in Graphcore's growth
- Free food and on-site barista at the Bristol office
- Income protection and life assurance
- Optional private medical insurance
- Optional dental cover
- Health cash plan
- Cycle-to-work scheme
- Give-as-you-earn payroll giving
Location and Working Arrangement
This position is based in Bristol, UK. The listing does not specify a hybrid or remote option, so candidates should treat it as on-site and confirm the exact working arrangement with Graphcore during the application process. No information about visa sponsorship or relocation assistance is stated in the listing; candidates who require either should raise this with the recruiting team before investing significant time in the hiring process.